Autonomous fault emulation: a new FPGA-based acceleration system for hardness evaluation

The appearance of nanometer technologies has produced a significant increase of integrated circuit sensitivity to radiation, making the occurrence of soft errors much more frequent, not only in applications working in harsh environments, like aerospace circuits, but also for applications working at the earth surface. Therefore, hardened circuits are currently demanded in many applications where fault tolerance was not a concern in the very near past. To this purpose, efficient hardness evaluation solutions are required to deal with the increasing size and complexity of modern VLSI circuits. In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented. The proposed approach uses FPGA emulation in an autonomous manner to fully exploit the FPGA emulation speed. Three different techniques to implement it are proposed and analyzed. Experimental results show that the proposed Autonomous Emulation approach can reach execution rates higher than one million faults per second, providing a performance improvement of two orders of magnitude with respect to previous approaches. These rates give way to consider very large fault injection campaigns that were not possible in the past.This work was supported by the Directorate of Research of Madrid Community Government, Spain (Code 07/0052/2003 2) and by the European Commission and Spanish Government under MEDEA+ Project (PARACHUTE-2A701) and PROFIT Project (CIRCE-FIT-330100-2005-60)

Extensive SEU impact analysis of a PIC microprocessor for selective hardening

In order to increase the robustness of a circuit against SEUs, fault injection is commonly used to locate weak areas. autonomous emulation is a very powerful tool to locate these areas by executing huge fault injection campaigns. In this work, fault injection has been extensively applied to a PIC18 microprocessor, while executing three different workloads. A 80 million fault campaign has been performed, and results show that a failure rate lower than 1% can be obtained by hardening a 24% of the circuit flip-flops, for the given applications

Partial TMR in FPGAs Using Approximate Logic Circuits

TMR is a very effective technique to mitigate SEU effects in FPGAs, but it is often expensive in terms of FPGA resource utilization and power consumption. For certain applications, Partial TMR can be used to trade off the reliability with the cost of mitigation. In this work we propose a new approach to build Partial TMR circuits for FPGAs using approximate logic circuits. This approach is scalable, with a fine granularity, and can provide a flexible balance between reliability and overheads. The proposed approach has been validated by the results of fault injection experiments and proton irradiation campaigns.This work was supported in part by the Spanish Ministry of Economy and Competitiveness under contract ESP2015-68245-C4-1-P

HW/SW Co-Simulation System for Enhancing Hardware-in-the-Loop of Power Converter Digital Controllers

Digital controllers of power converters are more and more implemented in FPGAs due to the increasing complexity of current control algorithms, higher switching frequencies, and concurrence requirements. System behavior depends not only on the control algorithm but also on the implementation issues. Thus, closed-loop controller evaluation at early design stages is a main concern. In this paper, a new hardware-in-the-loop method is proposed. It profits from FPGAs and their design tools in order to validate the closed-loop power converter before prototyping the power stage. The proposed solution presents a general architecture that does not depend on specific vendors or CAD tools, but it uses those utilized for the final implementation of the controller. A case study is presented with a given implementation of the proposed solution. Comparisons with existing alternatives show the advantages of our approach

SEU Sensitivity Comparison for Different Reprogrammable Technologies With Minority Check Block

In this work, a method is proposed for obtaining comparable measurements of the SEU sensitivity in reprogrammable devices that present different characteristics like internal architecture, technology, amount of available resources, etc. A specific minority checker is developed for reporting the presence of SEUs or MBUs which will help in this comparing task during dynamic tests.This work was supported in part by the Spanish Ministry of Science and Technology, code TEC2010-22095-C03-03. RENASER+ projec

Hardware Fault Injection

Hardware fault injection is the widely accepted approach to evaluate the behavior of a circuit in the presence of faults. Thus, it plays a key role in the design of robust circuits. This chapter presents a comprehensive review of hardware fault injection techniques, including physical and logical approaches. The implementation of effective fault injection systems is also analyzed. Particular emphasis is made on the recently developed emulation-based techniques, which can provide large flexibility along with unprecedented levels of performance. These capabilities provide a way to tackle reliability evaluation of complex circuits.Publicad

Solar Energy Harvesting to Improve Capabilities of Wearable Devices

The market of wearable devices has been growing over the past decades. Smart wearables are usually part of IoT (Internet of things) systems and include many functionalities such as physiological sensors, processing units and wireless communications, that are useful in fields like healthcare, activity tracking and sports, among others. The number of functions that wearables have are increasing all the time. This result in an increase in power consumption and more frequent recharges of the battery. A good option to solve this problem is using energy harvesting so that the energy available in the environment is used as a backup power source. In this paper, an energy harvesting system for solar energy with a flexible battery, a semi-flexible solar harvester module and a BLE (Bluetooth® Low Energy) microprocessor module is presented as a proof-of-concept for the future integration of solar energy harvesting in a real wearable smart device. The designed device was tested under different circumstances to estimate the increase in battery lifetime during common daily routines. For this purpose, a procedure for testing energy harvesting solutions, based on solar energy, in wearable devices has been proposed. The main result obtained is that the device could permanently work if the solar cells received a significant amount of direct sunlight for 6 h every day. Moreover, in real-life scenarios, the device was able to generate a minimum and a maximum power of 27.8 mW and 159.1 mW, respectively. For the wearable system selected, Bindi, the dynamic tests emulating daily routines has provided increases in the state of charge from 19% (winter cloudy days, 4 solar cells) to 53% (spring sunny days, 2 solar cells). Keywords: energy harvesting; internet of things; physiologicalThis research was funded by the Department of Research and Innovation of Madrid Regional Authority, in the EMPATIA-CM research project (reference Y2018/TCS-5046). This work has been partially supported by the European Union—NextGenerationEU, with the SAPIENTIAE4BINDI project “Proof of Concept” 2021. (Ref: PDC2021-121071-I00/AEI/10.13039/501100011033). This work has been supported by the Madrid Government (Comunidad de Madrid-Spain) under the Multiannual Agreement with UC3M in the line of Excellence of University Professors (EPUC3M26), and in the context of the V PRICIT (Regional Programme of Research and Technological Innovation)

Error Detection and Mitigation of Data-Intensive Microprocessor Applications Using SIMD and Trace Monitoring

This article proposes a software error mitigation approach that uses the single instruction multiple data (SIMD) coprocessor to accelerate computation over redundant data. In addition, an external IP connected to the microprocessor's trace interface is used to detect errors that are difficult to cover with software-implemented techniques. The proposed approach has been implemented in an ARM microprocessor, and an irradiation campaign with neutrons has been carried out at Los Alamos National Laboratory. Experimental results demonstrate the high error coverage (more than 99.9%) of the proposed approach. The neutron cross section of errors that were not corrected nor detected was reduced by more than three orders of magnitude

The Use of Microprocessor Trace Infrastructures for Radiation-Induced Fault Diagnosis

This work proposes a methodology to diagnoseradiation-induced faults in a microprocessor using the hardwaretrace infrastructure. The diagnosis capabilities of this approachare demonstrated for an ARM microprocessor under neutronand proton irradiation campaigns. The experimental resultsdemonstrate that the execution status in the precise moment thatthe error occurred can be reconstructed, so that error diagnosiscan be achieved